1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, the present invention relates to a semiconductor memory device and a method of a defective cell test that can examine a precise detection test for the defective cell.
Priority is claimed on Japanese Patent Application No. 2007-280754, filed Oct. 29, 2007, the content of which is incorporated herein by reference.
2. Description of Related Art
In a dynamic random access memory (DRAM), the number of memory cells is too large to produce all memory cells completely. Therefore, there is a case in which a few memory cells have a poor storage capacitance due to production problems. For such memory cells having a defect, it is important to reliably detect the defect in a test process. If the defect can be detected, the defective cell can be exchanged for a cell with no defects. Even though the test process is performed after the exchanging process, a release of the rejected product can be prevented if a defect is detected.
An operation of the memory cell having a poor storage capacitance is described hereinafter for the case in which a word line is actually activated and data is output to a sense amplifier. FIG. 12 shows a timing chart in the case that a memory cell portion obtains an initial voltage of 0 V.
As shown in FIG. 12, when the word line is activated from 0 V (GND level) to a word voltage VPP, memory cell data is leaked to a bit line. In this case, since the defective cell has few cell capacitances and the quantity of electric charge is small, the bit line voltage of the defective cell is reduced slightly.
On the other hand, since a normal cell has a sufficiently large capacitance and the quantity of electric charge thereof is large, a bit line voltage of the normal cell is highly reduced compared to the defective cell. As a result, a differential voltage of the bit line voltage from a voltage of bit line reference (VBLR) is quite small for the defective cell, while the differential voltage is large enough for the normal cell.
As described above, it is revealed that the differential voltage of the bit line is different for the normal cell and the defective cell. If the differential voltage is large, operation of the sense amplifier becomes stable. However, if the differential voltage is small, the operation of the sense amplifier becomes unstable. In some cases, the sense amplifier may fail to operate, and read data which has inverted logic.
However, since the bit line voltage of the defective cell is passably lower than the VBLR as shown in FIG. 12, the sense amplifier may operate as desired. This means that the defective cell cannot be detected in the actual test process.
Since the defective cell may induce an incorrect operation of the sense amplifier, the defective cell should be reliably detected during the test process. For this reason, the test under an accelerated condition that easily induces a failure is generally examined. There are many types of the test mode that provides the accelerated condition during the DRAM test. In order to reliably induce an incorrect operation of the sense amplifier when the differential voltage is small, there is a method that changes the VBLR level.
When the VBLR level is changed, the differential voltage which is received by the sense amplifier during the read out operation is changed. For such a case, the differential voltage is described hereinafter. Based on charge conservation law, the following equation (1) is derived as;Cs×Vs+Cb×VBLR=(Cs+Cb)×Vb  (1).
Therefore, the differential voltage ΔV is obtained as;
                                                                        Δ                ⁢                                                                  ⁢                V                            =                                                                VBLR                  -                  Vb                                                                                                                                        =                                                                        VBLR                    -                                                                  (                                                                              Cs                            ×                            Vs                                                    +                                                      Cb                            ×                            VBLR                                                                          )                                            /                                              (                                                  Cs                          +                          Cb                                                )                                                                                                                          ,                                                          (        2        )            where Cs is the cell capacitance, Cb is the bit line capacitance, Vs is the cell voltage, VBLR is the bit line stand-by voltage, and Vb is the bit line voltage after activating the word line.
In the case of reading out L-data, the cell voltage Vs can be set to 0 V, hence, the differential voltage ΔVL is obtained as;ΔVL=VBLR×Cs/(Cs+Cb)  (3).
In the case of reading out H-data, the cell voltage Vs is set to Va, hence, the differential voltage ΔVH is obtained as;ΔVH=(Va−VBLR)×Cs/(Cs+Cb)  (4).
From Eq. (3), for the case of reading out L-data, the differential voltage ΔVL becomes low through the VBLR being set low, so that the accelerated condition can be realized. On the other hand, for the case of reading out H-data, from Eq. (4), the differential voltage ΔVH becomes low through the VBLR being set high, so that the accelerated condition can be realized.
A semiconductor memory device that enables simultaneous read-out through a bit line shared by a plurality of cells is disclosed in Japanese Patent No. 2732762. A semiconductor memory device that includes a circuit generating a reference voltage is disclosed in Japanese Unexamined Patent Application, First Publication, No. 2005-339590. A semiconductor memory device that simultaneously activates a plurality of word lines is disclosed in Japanese Unexamined Patent Application, First Publication, No. 2006-260735. However, the prior art fails to disclose a semiconductor memory device that examines the defective cell test under the accelerated condition by changing the voltage of bit line reference.
According to the conventional failure detection test in the semiconductor memory device, there has explained the method, in the case of reading out the cell by the acceleration, that provides the accelerated condition in which the differential voltage is smaller during the sense amplifier operation than that of an usual operation by changing the VBLR, so as to examine the failure detection test.
Even if the accelerated condition is applied, although the differential voltage decreases, the differential voltage does not invert to the reference voltage. The invert means that the bit line voltage is higher or lower than the reference voltage when the L-data or the H-data is read out. Accordingly, since the sense amplifier correctly operates, the defective cell may not be detected. Particularly, since the cell capacitance Cs of the defective cell is small, it is revealed from Eqs. (3) and (4), in this case, that the effect of the accelerated condition by changing the VBLR on the differential voltage is small.